The liquid crystal display panel is formed by a two dimensional liquid crystal pixel matrix; the driving device of the liquid crystal display panel comprises a gate driving device and a data driving device. The data driving device latches the inputted display data in order and converts them into analog signals, the data lines of the liquid crystal display panel are scanned sequentially; the gate driving device comprises several shift register units, the signal at the control signal output end of each stage of shift register unit will be transmitted to the reset signal input end of its previous stage of shift register unit and the control signal input end of its next stage of shift register unit. Each stage of shift register unit converts the inputted clock signal into an open signal or a close signal, which is outputted from its control signal output end to a gate line corresponding to it.
The typical structure in the existing shift register unit is as shown in FIG. 1, FIG. 2 is a working sequence diagram of the shift register unit as shown in FIG. 1. Its working principle is as follows:
In the first phase, the control signal input end INPUT is of high potential, the reset signal input end RESETIN is of low potential, the transistor T103 is turned on, the transistor T101, the transistor T102, and the transistor T104 are cut-off, the capacitor C102 is charged through the transistor T103, hence, the connection point P is of high potential;
In the second phase, the control signal input end INPUT is of low potential, the reset signal input end RESETIN is of low potential, the clock signal input end CLKIN is of high potential, the transistor T101 is turned on, hence, the control signal output end OUTPUT outputs a high level signal; since the transistor T102, the transistor T103, and the transistor T104 are cut-off, the connection point P is floating here, the control signal output end OUTPUT is of high potential, and is coupled to the connection point P through the capacitor C102, so the potential at the connection point P continues to rise on the basis of the first phase;
In the third phase, the control signal input end INPUT is of low potential, the reset signal input end RESETIN inputs a high level signal, the transistors T102 and T104 are turned on, the transistor T101 and the transistor T103 are cut-off, the capacitor C102 is discharged, the connection point P is of low potential, since the source of T102 is connected with the low voltage signal input VSSIN, the control signal output end OUTPUT is of low potential;
In the fourth phase, the control signal input end INPUT is of low potential, the reset signal input end RESETIN is of low potential, hence, the transistor T101, the transistor T102, the transistor T103 and the transistor T104 are all cut-off, the signal outputted by the control signal output end OUTPUT remains at a low potential;
In the fifth phase, the signal inputted by the control signal input end INPUT is of low potential, the reset signal input end RESETIN is of low potential, the transistor T101, the transistor T102, the transistor T103 and the transistor T104 remain in the state of the fourth stage, hence, the control signal output end OUTPUT is still of low potential.
In these five phases: in the first phase, control signal input end INPUT is inputted a high level signal; in the second phase, control signal output end OUTPUT outputs a high level signal, thus a shift is completed; in the third phase, reset signal input end RESETIN is inputted a high level signal to complete the reset operation; hence, the first, second and third phases can be defined as the working time of the shift register unit, the fourth and the fifth phases can be defined as the non-working time of the shift register unit.
It can be seen that in the non-working time, the control signal input end INPUT, the reset signal input end RESETIN and the control signal output end OUTPUT are all of low level; when the clock signal input end CLKIN is of high potential, it will be coupled to the connection point P through a parasitic capacitance between the gate and the drain of the transistor T101, such that the leakage current of the transistor T101 is increased, which results in rising of the potential of the control signal output end OUTPUT; moreover, since the transistor T103, the transistor T104 and the transistor T102 are all cut-off in the non-working time, the voltage of the control signal output end OUTPUT cannot be reduced, thereby enabling the output signal of the control signal output end OUTPUT to produce a relatively large coupled noise.
To sum up, in the non-working time of the existing shift register unit, when the received clock signal is of high level, the high level signal will be coupled to the output end of the shift register unit through a parasitic capacitance on the transistor, while the output end is in a floating state in the non-working time, such that the noise coupled to the output end of the shift register unit by the high level signal cannot be eliminated, and the noise will be outputted together with the signal of the output end of the shift register unit, which results in relatively large noise in the signal outputted by the shift register unit.